CppCon 2014

Emerging programming models, and their implementations will benefit from taking a strong applications perspective when validating the true applicability of the proposed technical specifications of solutions such as C++17 proposed standard.  In order to provide an applications perspective to drive a vertically integrated discussion, as a context, the core data structures, algorithms and parallel programming model utilized by the open source Stanford SU2 multi-physics C++ based toolkit, will be described in detail.  The objective of  the proposed “Open-Content”  session is  to foster  a  lively holistic discussion intertwining  a realistic
application context around important emerging topics including pertinent to C++17 including:
•  Does C++17 TM proposal’s proposed productivity gains mitigate it’s performance implications?
•  Does C++17 sufficiently enable cache-conscious programming?
•  How does C++17 enable scalability and
•  What lessons can C++17 learn from the DARPA HPCS language efforts?

The numerical solution of systems of partial differential equations or “coupled-multi-physics” simulations, is an important  application  area  for  academic,  governmental  and  industry  organizations  in  the  science, engineering and medical communities.  These organizations often utilize large-scale computing platforms to solve ever larger and more complex modeling and simulation problems. Consequently, the games and film industry over the past decade has been rapidly increasing the scope and resolution of their simulation models to feed their ever increasing demand of visual realism in games and feature-film visual effects.
In the past, heterogeneity has largely been at the Node level (i.e. single blade), with communication from the CPU to the Accelerator (many-core CPU, GPU / FPGA / DSP, etc.) through the PCIe protocol and it’s variants. In the near future, socket-level communication technologies such as Intel’s KTI or the IBM CAPI / Nvidia NVLink protocol, will enable accelerators to become equal piers to the main CPU, dramatically reducing  latency of  communication.  By  the  2017  timeframe,  it  is  likely  that  Accelerators  will  be  fully
integrated into the main CPU. Furthermore, to address memory access latency, bandwidth and IO, a range of  memory  technologies  are  emerging  including:  DDR4  memory,  on-package stacked high-bandwidth memory  and  non-volatile  memory  (i.e.  memory-channel  /  Flash)  technologies.   Finally,  large-scale compute servers for public / private clouds will aggregate these technologies and likely introduce silicon nano-photonics interconnects, further reducing the latency of communication while increasing bandwidth.
As we approach the “exascale” computing systems we can imagine 100s of cores in a single chip, with aggregate capabilities of 10 ^18th power flops / second, or roughly 1,000 fold performance of current systems.

Today it  is  a  “un-spoken”  truth that when  practically  applying  scalable  systems  utilizing heterogeneous computing, a substantial amount of computing resources are often left under-utilized due to the in-effective utilization  of  the  memory  hierarchy by the applications,  their underlying  libraries,  programming  models and supporting system software and hardware.  Furthermore as the simulation problem size increases, and the  modeling  of  “dynamic  systems”  becomes  important,  unstructured  adaptive  methods  (enabling  a simulation-level-of-detail) will become more important. Subsequently, it is likely that these applications
will require pointer-based data structures, dynamic memory allocation and irregular parallelism.